Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
IEEE Transactions on Computers
A reconfigurable and fault-tolerant VLSI multiprocessor array
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Self-Diagnosis of Failures in VLSI Tree Array Processors
IEEE Transactions on Computers
IEEE Transactions on Computers
Fault-Tolerant Interleaved Memory Systems with Two-Level Redundancy
IEEE Transactions on Computers
Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy
IEEE Transactions on Computers
A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits
IEEE Transactions on Computers
IEEE Transactions on Computers
Routing in Modular Fault-Tolerant Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
Spare processor allocation for fault tolerance in torus-based multicomputers
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
A dynamically reconfigurable interconnect for array processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Reconfiguration schemes for replacing faulty cells (processing elements) with spare cells are introduced for massive parallel rectangular mesh array processors with fine-grained cells. The authors introduce the concept of two-level redundancy as an effective way of using redundant units to reduce the complexity of reconfiguration control circuitry, to limit the length of connecting wires after reconfiguration, and to increase the manufacturing yield and the operation reliability. An optimization technique for allocating the redundant cells into both levels is presented. The operational reliability and manufacturing yield of arrays with two-level redundancy are presented. The yield estimation problem is modeled by an occupancy problem in classical combinatorial analysis. Both distributed and clustered defects are taken into consideration in the yield estimation.