Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems

Authors:
Israel Koren;Dhiraj K. Pradhan
Affiliations:
Univ. of Massachusetts, Amherst;Univ. of Massachusetts, Amherst
Venue:
IEEE Transactions on Computers
Year:
1987

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Abstract

The incorporation of different forms of redundancy has been recently proposed for various VLSI and WSI designs. These include regular architectures, built by interconnecting a large number of a few types of system elements on a single chip or wafer. The motivation for introducing fault-tolerance (redundancy) into these architectures is two-fold: yield enhancement and performance (like computational availability) improvement.