Yield optimization in wafer scale circuits with hierarchical redundancies
Integration, the VLSI Journal
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
IEEE Transactions on Computers
Architectural Yield Optimization for WSI
IEEE Transactions on Computers
Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy
IEEE Transactions on Computers
Applying dynamic reconfiguration for fault tolerance in fine-grained logic arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a method to accelerate the search for the number of spares to be included in defect tolerant integrated circuits. Our method is obtained by bringing two modifications to a conventional evaluation method. The main motivations behind the development of this method are: the possibilities offered by the implementation of defect tolerance, the existence of many yield models, which may predict different results in terms of optimum number of spares, and the fact that some models are very compute intensive. The modeling methods leading to several usual yield models are briefly presented. We also present results showing that our method is valid for a wide range of parameters. However, this method can be applied to all yield models considered and it can significantly reduce the time spent in the search for the best possible reconfiguration strategies.