Efficiently supporting fault-tolerance in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
On-line fault detection for bus-based field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Configuration of Locally Spared Arrays in the Presence of Multiple Fault Types
IEEE Transactions on Computers
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits
IEEE Transactions on Computers
Implementation Approaches for Reconfigurable Logic Applications
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
RACE: Reconfigurable and Adaptive Computing Environment
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
The swappable logic unit: a paradigm for virtual hardware
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Temporal Partitioning and Scheduling for Reconfigurable Computing
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Design and reliability challenges in nanometer technologies
Proceedings of the 41st annual Design Automation Conference
Design Concepts for a Dynamically ReconfigurableWireless Sensor Node
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Fault-tolerance in nanocomputers: a cellular array approach
IEEE Transactions on Nanotechnology
An approach to test determination for programmable logic arrays
AIC'09 Proceedings of the 9th WSEAS international conference on Applied informatics and communications
Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
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This paper presents the realization of a fault tolerance technique for a dynamically reconfigurable array of programmable cells. The three parts of the technique, fault detection, fault reconfiguration, and fault recovery, are implemented completely in hardware and form a self-contained system. Each of the parts can be exchanged by an alternative implementation without affecting the remaining parts too much, thus making the concept adaptable to different reconfigurable circuits. A hardware realization for the core mechanism is discussed and a prototypical design of a field-programmable gate array implementing the complete system is described. The technological development towards nanoscale feature sizes and the growing influence of deep-submicrometer effects will result in an inherent unreliability of the individual components of future circuit implementations and a higher vulnerability towards external influences. The technique discussed can be used to exploit dynamic reconfiguration capabilities of programmable arrays to alleviate system vulnerability towards these effects and thus to enhance their overall reliability.