Memory products
Fault tolerant arrays
IEEE Transactions on Computers
A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits
IEEE Transactions on Computers
A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing
IEEE Transactions on Parallel and Distributed Systems
Feasible Regions Quantify the Configuration Power of Arrays with Multiple Fault Types
EDCC-1 Proceedings of the First European Dependable Computing Conference on Dependable Computing
An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors
EDCC-1 Proceedings of the First European Dependable Computing Conference on Dependable Computing
Computational Aspects of VLSI
Graphs and Hypergraphs
Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
What Designers of Bus and Network Architectures Should Know about Hypercubes
IEEE Transactions on Computers
Applying dynamic reconfiguration for fault tolerance in fine-grained logic arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 14.98 |
The bulk of results for the performance of configuration architectures treat the case of failed processors, but neglect switches that are stuck open or closed. By contrast, the present work characterizes this multivariate problem in the presence of either iid or clustered faults. Suppose that the designer wishes to assure, with high probability, a fault free $s \times t$ array. If local sparing is used then, as we prove, the area of the redundant array is 1) $\Theta(st\; \log st)$ in the presence of faulty elements or faulty elements and switches stuck open; 2) $\Theta(st\; \log^2 st)$ in the presence of faulty elements and switches stuck closed; 3) $\Theta([st]^2\; \log st)$ in the presence of faulty elements and switches that may be either stuck open or stuck closed. We also furnish bounds on maximum wirelength and an optimal configuration algorithm.