Correlation analysis of particle clusters on integrated circuit wafers
IBM Journal of Research and Development
Modeling Defect Spatial Distribution
IEEE Transactions on Computers
Small-area fault clusters and fault tolerance in VLSI circuits
IBM Journal of Research and Development
A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors
IEEE Transactions on Computers
Configuration of Locally Spared Arrays in the Presence of Multiple Fault Types
IEEE Transactions on Computers
Incorporating Yield Enhancement into the Floorplanning Process
IEEE Transactions on Computers
Accurate yield estimation of circuits with redundancy
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
An Improved Analytical Yield Evaluation Method for Redundant RAM's
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Constructive Floorplanning with a Yield Objective
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Should Yield be a Design Objective?
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Predicting Defect-Tolerant Yield in the Embedded Core Context
IEEE Transactions on Computers
Wafer-level modular testing of core-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fuzzy neural network approach for die yield prediction of wafer fabrication line
FSKD'09 Proceedings of the 6th international conference on Fuzzy systems and knowledge discovery - Volume 3
Economic analysis of testing homogeneous Manycore chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The effect on quality of non-uniform fault coverage and fault probability
ITC'94 Proceedings of the 1994 international conference on Test
A statistical study of defect maps of large area VLSI IC's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An ROBDD-based combinatorial method for the evaluation of yield of defect-tolerant systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling the impact of permanent faults in caches
ACM Transactions on Architecture and Code Optimization (TACO)
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It has been recognized that the yield of fault-tolerant VLSI circuits depends on the size of the fault clusters. Consequently, models for yield analysis have been proposed for large-area clustering and small-area clustering, based on the two-parameter negative-binomial distribution. The addition of a new parameter, the block size, to the two existing parameters of the fault distribution is proposed. This parameter allows the unification of the existing models and, at the same time, adds a whole range of medium-size clustering models. Thus, the flexibility in choosing the appropriate yield model is increased. Methods for estimating the newly defined block size are presented and the approach is validated through simulation and empirical data.