Economic analysis of testing homogeneous Manycore chips

Authors:
Lin Huang;Qiang Xu
Affiliations:
CURE Laboratory, Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong;CURE Laboratory, Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong and Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2010

Citing 18
Cited 0

A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits

IEEE Transactions on Computers
Cost and benefit models for logic and memory BIST

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Modeling the Economics of Testing: A DFT Perspective

IEEE Design & Test
Embedded Software-Based Self-Test for Programmable Core-Based Designs

IEEE Design & Test
CMOS IC reliability indicators and burn-in economics

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Too much delay fault coverage is a bad thing

Proceedings of the IEEE International Test Conference 2001
Cost Model Analysis of DFT Based Fault Tolerant SOC Designs

ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
A two-level scheduling method: an effective parallelizing technique for uniform nested loops on a DSP multiprocessor

Journal of Systems and Software - Special issue: Software engineering education and training
Industry Trends: Chip Makers Turn to Multicore Processors

Computer
Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation

IEEE Micro
Reducing Burn-in Time through High-Voltage Stress Test and Weibull Statistical Analysis

IEEE Design & Test
Systematic software-based self-test for pipelined processors

Proceedings of the 43rd annual Design Automation Conference
Computer Architecture, Fourth Edition: A Quantitative Approach

Computer Architecture, Fourth Edition: A Quantitative Approach
A robust protocol for concurrent on-line test (COLT) of NoC-based systems-on-a-chip

Proceedings of the 44th annual Design Automation Conference
How Many Test Patterns are Useless?

VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Defect tolerance in homogeneous manycore processors using core-level redundancy with unified topology

Proceedings of the conference on Design, automation and test in Europe
Lifetime reliability-aware task allocation and scheduling for MPSoC platforms

Proceedings of the Conference on Design, Automation and Test in Europe
On Task Allocation and Scheduling for Lifetime Extension of Platform-Based MPSoC Designs

IEEE Transactions on Parallel and Distributed Systems

Quantified Score

Hi-index	0.03

Visualization

Abstract

The employment of a large number of structurally identical cores on a single silicon die is generally regarded as a promising solution for tera-scale computation, known as manycore chips. To ensure the product quality of such complex integrated circuits before shipping them to final users, extensive manufacturing tests are necessary and the associated test cost can account for a large share of the total production cost. By introducing spare cores on-chip, the burn-in test time can be shortened and the defect coverage requirements for core tests can be also relaxed, without sacrificing quality of the shipped products. If the above test cost reduction exceeds the manufacturing cost of the extra cores, the total production cost of manycore chips can be reduced. In this paper, we develop novel analytical models to study the above tradeoff and we verify the effectiveness of the proposed test economics model for hypothetical manycore chips with various configurations.