Too much delay fault coverage is a bad thing

Effects of Multi-cycle Sensitization on Delay Tests

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

On Selecting Testable Paths in Scan Designs

Journal of Electronic Testing: Theory and Applications

Speed Binning with Path Delay Test in 150-nm Technology

IEEE Design & Test

Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs

IEEE Design & Test

Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings

IEEE Design & Test

On the generation of scan-based test sets with reachable states for testing under functional operation conditions

Proceedings of the 41st annual Design Automation Conference

Delay Fault Testing of Core-Based Systems-on-a-Chip

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Efficient techniques for transition testing

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Detection of multiple transitions in delay fault test of SPARC64 microprocessor

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Delay defect screening for a 2.16GHz SPARC64 microprocessor

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Constraint extraction for pseudo-functional scan-based delay testing

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs

IEEE Transactions on Computers

On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan

IEEE Transactions on Computers

Functional constraints vs. test compression in scan-based delay testing

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Improving Transition Delay Test Using a Hybrid Method

IEEE Design & Test

Functional Constraints vs. Test Compression in Scan-Based Delay Testing

Journal of Electronic Testing: Theory and Applications

A Methodology for Handling Complex Functional Constraints for Large Industrial Designs

Journal of Electronic Testing: Theory and Applications

Improving the transition fault coverage of functional broadside tests by observation point insertion

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

Journal of Electronic Testing: Theory and Applications

Conflict driven scan chain configuration for high transition fault coverage and low test power

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

On systematic illegal state identification for pseudo-functional testing

Proceedings of the 46th Annual Design Automation Conference

Functional broadside tests under an expanded definition of functional operation conditions

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Double-single stuck-at faults: a delay fault model for synchronous sequential circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

TOV: sequential test generation by ordering of test vectors

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A novel test application scheme for high transition fault coverage and low test cost

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip

Hazard-based detection conditions for improved transition fault coverage of scan-based tests

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Economic analysis of testing homogeneous Manycore chips

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Reducing the storage requirements of a test sequence by using a background vector

Proceedings of the Conference on Design, Automation and Test in Europe

On reset based functional broadside tests

Proceedings of the Conference on Design, Automation and Test in Europe

On the relationship between stuck-at fault coverage and transition fault coverage

Proceedings of the Conference on Design, Automation and Test in Europe

Functional and partially-functional skewed-load tests

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Chiba Scan Delay Fault Testing with Short Test Application Time

Journal of Electronic Testing: Theory and Applications

Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Built-in generation of functional broadside tests using a fixed hardware structure

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

RTL analysis and modifications for improving at-speed test

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe

A Simulated Annealing Inspired Test Optimization Method for Enhanced Detection of Highly Critical Faults and Defects

Journal of Electronic Testing: Theory and Applications

Built-in generation of multicycle functional broadside tests with observation points

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Virtually-aged sampling DMR: unifying circuit failure prediction and circuit failure detection

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

Design-for-testability for multi-cycle broadside tests by holding of state variables

ACM Transactions on Design Automation of Electronic Systems (TODAES)