An efficient non-enumerative method to estimate path delay fault coverage
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Fastpath: A Path-Delay Test Generator for Standard Scan Designs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Testing of critical paths for delay faults
Proceedings of the IEEE International Test Conference 2001
Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
On test coverage of path delay faults
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Segment delay faults: a new fault model
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Selection of Potentially Testable Path Delay Faults for Test Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Efficient Method to Identify Untestable Path Delay Faults
ATS '01 Proceedings of the 10th Asian Test Symposium
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path delay test compaction with process variation tolerance
Proceedings of the 42nd annual Design Automation Conference
A dynamic test compaction procedure for high-quality path delay testing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Path selection for transition path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Input necessary assignments for testing of path delay faults in standard-scan circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test compaction for small-delay defects using an effective path selection scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the optimality of K longest path generation algorithm under memory constraints
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents a new model for gate-to-channel GOS defects. The transistors used in digital cell library are usually designed with a minimum-size. This new model permits to handle minimal-length transistors allowing the simulation of GOS defects ...