Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test challenges for deep sub-micron technologies
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Efficient Identification of Non-Robustly Untestable Path Delay Faults
Proceedings of the IEEE International Test Conference
Compact two-pattern test set generation for combinational and full scan circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Generation of Compact Delay Tests by Multiple-Path Activation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
High Quality Robust Tests for Path Delay Faults
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Selection of Potentially Testable Path Delay Faults for Test Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Finding a Small Set of Longest Testable Paths that Cover Every Gate
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On Selecting Testable Paths in Scan Designs
Journal of Electronic Testing: Theory and Applications
Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults
Proceedings of the conference on Design, automation and test in Europe
A Postprocessing Procedure of Test Enrichment for Path Delay Faults
ATS '04 Proceedings of the 13th Asian Test Symposium
A Critical Path Selection Method for Delay Testing
ITC '04 Proceedings of the International Test Conference on International Test Conference
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A dynamic test compaction procedure for high-quality path delay testing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation
Journal of Electronic Testing: Theory and Applications
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In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths selected with a criterion. While the proposed method generates each two-pattern test for more than one fault in the target fault list as well as ordinary test compaction methods, secondary target faults are selected from the fault list such that many other faults, which may not be included in the fault list, are detected by the test pattern. Even if faults on long paths in a manufactured circuit are not included in the fault list due to a process variation or noise, the compact test set would detect the longer untargeted faults, i.e., the test set has a noise or variation tolerant nature. Experimental results show that the proposed method can generate a compact test set and it detects longer untargeted path delay faults efficiently.