A Critical Path Selection Method for Delay Testing

Authors:
Saravanan Padmanaban;Spyros Tragoudas
Affiliations:
Intel Corporation, Hillsboro, OR;Southern Illinois University, Carbondale, IL
Venue:
ITC '04 Proceedings of the International Test Conference on International Test Conference
Year:
2004

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Abstract

An approach for selecting critical paths along which testable path delay faults can exist is presented. The proposed method is particularly helpful on path intensive circuits. Critical paths are selected implicitly with the aid of a combination of decision diagrams. An implicit method to eliminate untestable faults along the selected paths is also presented. The effectiveness of the approach is demonstrated on path intensive ISCAS'85, ISCAS'89 and ITC'99 benchmarks.