Input necessary assignments for testing of path delay faults in standard-scan circuits

Authors:
Irith Pomeranz;Sudhakar M. Reddy
Affiliations:
School of Electrical and Computer Engineering, Purdue University, W. Lafayette, IN;Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2011

Citing 9
Cited 1

Fast identification of robust dependent path delay faults

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Fast identification of untestable delay faults using implications

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Path selection and pattern generation for dynamic timing analysis considering power supply noise effects

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths

VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
High Quality Robust Tests for Path Delay Faults

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Selection of Potentially Testable Path Delay Faults for Test Generation

ITC '00 Proceedings of the 2000 IEEE International Test Conference
On Selecting Testable Paths in Scan Designs

Journal of Electronic Testing: Theory and Applications
A Critical Path Selection Method for Delay Testing

ITC '04 Proceedings of the International Test Conference on International Test Conference
Definition and application of approximate necessary assignments

Proceedings of the 19th ACM Great Lakes symposium on VLSI

Computing two-pattern test cubes for transition path delay faults

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

We consider the use of necessary assignments for input lines, referred to as input necessary assignments, as part of a test generation process for path delay faults in standard-scan circuits. Input necessary assignments are computed in polynomial time and provide a unified framework for identifying undetectable faults and generating tests for detectable faults. Within this framework, large numbers of path delay faults can be considered efficiently and accurately. The proposed test generation procedure is able to resolve large numbers of path delay faults associated with the longest paths in benchmark circuits by detecting the faults using broadside tests or showing that they are undetectable by such tests. We also consider the use of input necessary assignments for test compaction.