Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Crosstalk Test Generation on Pseudo industrial Circuits: A Case Study
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Delay Testing Considering Power Supply Noise Effects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Delay Fault Testing of Core-Based Systems-on-a-Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Path delay test compaction with process variation tolerance
Proceedings of the 42nd annual Design Automation Conference
A dynamic test compaction procedure for high-quality path delay testing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Estimation of delay test quality and its application to test generation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Transition path delay faults: a new path delay fault model for small and large delay defects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Path selection for transition path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Input necessary assignments for testing of path delay faults in standard-scan circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Detailed circuit simulations have demonstrated that a classical two-pattern robust test for a path delay fault may not excite the worst case delay of the target path. We have developed a new definition of robust test that maintains the desirable properties of classical robust tests while incorporating two additional considerations, namely side-fan-in transitions and pre-initialization, which are shown to have a significant impact on the delay of the target path. The associated test generation problem was formulated as a constrained optimization problem, and an ATPG system developed to generate three-pattern robust tests that excite the worst case delay of the target path. The ATPG works on a gate level model that is augmented to capture the necessary switch level details. Experimental results show that the quality of robust delay tests varies dramatically and that the proposed high quality robust delay tests are needed for improving test quality.