MOS test pattern generation using path algebras
IEEE Transactions on Computers
Transistor level test generation for MOS circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Algorithms for Switch Level Delay Fault Simulation
Proceedings of the IEEE International Test Conference
DAC '77 Proceedings of the 14th Design Automation Conference
High Quality Robust Tests for Path Delay Faults
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Stuck-open and transition fault testing in CMOS complex gates
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Deception by Design: Fooling Ourselves with Gate-level Models
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Crosstalk Test Generation on Pseudo industrial Circuits: A Case Study
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Switch-level Delay Test of Domino Logic Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
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Gate-level models are usually used to generate testsfor circuits containing non-primitive CMOS gates.Itis shown that tests generated using these models andclassical conditions for robust path delay testing can failto detect delay faults in such circuits.A new delay-independent, switch-level delay test methodology, called\tau-robust testing, is proposed that defines new entitiescalled targets and proposes conditions to generate testsfor each target.It is proven that, under the assumeddelay model, a circuit that passes a test set containinga \tau-robust test for every target is guaranteed to operatecorrectly at the desired speed.The effectiveness of theproposed methodology is demonstrated by (a) illustratingthe difference between the delays excited by classicalrobust and \tau-robust tests via circuit simulation, and (b)generation of \tau-robust tests for benchmark circuits andcomparison of \tau-robust coverage of classical robust and\tau-robust test sets.