Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Universal delay test sets for logic networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust Path Delay-Fault Testability on Dynamic CMOS Circuits
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Critical Path Identification and Delay Tests of Dynamic Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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We address the testing of delay faults in domino circuits that contain complex gates. The different ways inwhich these faults can cause errors are demonstrated.We identify structures in both the evaluate and theprecharge logic that should be tested for delay faults.We propose conditions to generate delay tests for them,and outline extensions to handle mixed static-dominocircuits. Testability results are reported for benchmarkcircuits that are mapped to domino gates and in-housedomino circuits.