Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
TACO: timing analysis with coupling
Proceedings of the 37th Annual Design Automation Conference
A new gate delay model for simultaneous switching and its applications
Proceedings of the 38th annual Design Automation Conference
Switching window computation for static timing analysis in presence of crosstalk noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A new framework for static timing analysis, incremental timing refinement, and timing simulation
ATS '00 Proceedings of the 9th Asian Test Symposium
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
High Quality Robust Tests for Path Delay Faults
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Compact test sets for industrial circuits
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
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In this paper we present data that validates the viability of auniversity prototype crosstalk ATPG system, XGEN, on realdesigns. We remodeled Intel circuits and performed testgeneration using actual parasitic data. A crosstalk ATPGimplementation flow was developed based on Intel tools.Validation results are shown for the modified circuits. Criticalissues for preserving accurate timing information and capturingcrosstalk effects are discussed.