Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Testing of critical paths for delay faults
Proceedings of the IEEE International Test Conference 2001
Scan-Encoded Test Pattern Generation for BIST
Proceedings of the IEEE International Test Conference
On Generating High Quality Tests for Transition Faults
ATS '02 Proceedings of the 11th Asian Test Symposium
Simulator-oriented fault test generator
DAC '77 Proceedings of the 14th Design Automation Conference
High Quality Robust Tests for Path Delay Faults
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
An optimized BIST test pattern generator for delay testing
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
9.1 Efficient Path Selection for Delay Testing Based on Partial Path Evaluation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Selection of Potentially Testable Path Delay Faults for Test Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
On Selecting Testable Paths in Scan Designs
Journal of Electronic Testing: Theory and Applications
Longest path selection for delay test under process variation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
Transition path delay faults: a new path delay fault model for small and large delay defects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computing two-pattern test cubes for transition path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a path selection criterion to improve the coverage of small delay defects. Under this criterion, every line in the circuit is covered by one of the longest testable paths or subpaths that goes through it. Earlier criteria that considered only complete paths (from inputs to outputs) did not use longest testable subpaths, which may be longer than the longest complete testable paths. Earlier criteria that considered subpaths considered only subpaths of longest paths. We apply the proposed criterion to a delay fault model called the transition path delay fault model. This model was introduced to capture both small and large delay defects. We present experimental results to demonstrate that consideration of subpaths improves the circuit coverage relative to the case where only complete paths are allowed