Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Using a single input to support multiple scan chains
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
On identifying don't care inputs of test patterns for combinational circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Testing of critical paths for delay faults
Proceedings of the IEEE International Test Conference 2001
OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Segment delay faults: a new fault model
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
A Critical Path Selection Method for Delay Testing
ITC '04 Proceedings of the International Test Conference on International Test Conference
Path selection for transition path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Input necessary assignments for testing of path delay faults in standard-scan circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DYNAMITE: an efficient automatic test pattern generation system for path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
COMPACTEST: a method to generate compact test sets for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths
Proceedings of the Conference on Design, Automation and Test in Europe
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Considering full-scan circuits, incompletely-specified tests, or test cubes, are used for test data compression. When considering path delay faults, certain specified input values in a test cube are needed only for determining the lengths of the paths associated with detected faults. Path delay faults, and therefore, small delay defects, would still be detected if such values are unspecified. The goal of this paper is to explore the possibility of increasing the number of unspecified input values in a test set for path delay faults by unspecifying such values in order to make the test set more amenable to test data compression. Experimental results indicate that significant numbers of such values exist. The proposed procedure unspecifies them gradually to obtain a series of test sets with increasing numbers of unspecified values and decreasing path lengths. Experimental results also indicate that filling the unspecified values randomly (as with some test data compression methods) recovers some or all of the path lengths associated with detected path delay faults. The procedure uses a matching of the sets of detected faults for the comparison of path lengths.