The interdependence between delay-optimization of synthesized networks and testing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Linear Programming in Linear Time When the Dimension Is Fixed
Journal of the ACM (JACM)
Proceedings of the 39th annual Design Automation Conference
Test Generation for Global Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
9.1 Efficient Path Selection for Delay Testing Based on Partial Path Evaluation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Finding a Small Set of Longest Testable Paths that Cover Every Gate
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Timing Yield Estimation from Static Timing Analysis
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
PARADE: PARAmetric Delay Evaluation under Process Variation
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Path delay fault diagnosis and coverage-a metric and an estimation technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Statistical Fault Coverage Metric for Realistic Path Delay Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Variation-aware performance verification using at-speed structural test and statistical timing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Post-silicon timing characterization by compressed sensing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Critical Path Selection for Delay Testing Considering Coupling Noise
Journal of Electronic Testing: Theory and Applications
Hazard-based detection conditions for improved transition fault coverage of scan-based tests
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Path selection for transition path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay among all paths through that fault site. There are often multiple longest paths for each fault site in the circuit, due to different process conditions. To detect the smallest delay fault, it is necessary to test all longest paths through the fault site. However, previous methods are either inefficient or their results include too many paths that are not longest.This paper presents an efficient method to generate the longest path set for delay test under process variation. To capture both structural and systematic process correlation, we use linear delay functions to express path delays under process variation. A novel path-pruning technique is proposed to discard paths that are not longest, resulting in a significantly reduction in the number of paths compared with the previous best method. The new method can be applied to any process variation as long as its impact on delay is linear.