Proceedings of the 39th annual Design Automation Conference
On theoretical and practical considerations of path selection for delay fault testing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit?
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Longest path selection for delay test under process variation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Experience in critical path selection for deep sub-micron delay test and timing validation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
| Hi-index | 0.03 |
Published research on path delay fault (PDF) testing has largely focused on the PDF classification and test-vector generation problems. Little attention has been paid to the diagnosis of delay faults and in defining realistic metrics for delay-fault coverage, We present a statistical diagnosis framework to detect which parts of the circuit are likely to have caused a chip failure for a set of delay-fault tests. Under a model where distributed fabrication-process perturbations contribute to the occurrence of delay faults, we also find the associated likely fabrication-process parameter deviations from their nominal values as part of the diagnosis framework. We present results of experiments performed on some International Symposium on Circuits and Systems 1989 (ISCAS'89) benchmark circuits and also relate the slack of a path segment to its probability of contributing to the circuit failure. We also quantify the diagnosability of a PDF for a test and develop a methodology based on our statistical diagnosis framework to determine the diagnosability of each PDF detected by a given test set. We apply this approach to find the diagnosability of robust PDFs for the ISCAS'89 benchmark circuits. Furthermore, we propose a new and realistic definition of delay-fault coverage based on the percentage of fabricated faulty chips that can be detected as faulty by a given test set. This metric takes into account the probability distribution of delay-fault sizes caused by the chip manufacturing process as opposed to previously defined metrics that have been based primarily on the percentage of faults tested. We present a computationally viable scheme for using this metric to estimate the coverage of any given test set for a class of PDFs caused by distributed fabrication-process variations. We use the results for the ISCAS'89 benchmark circuits to demonstrate wide discrepancies between PDF coverage estimates for robust test sets obtained using our realistic definition and the ones obtained by using the traditional notion of coverage as the percentage of paths tested