A variable observation time method for testing delay faults
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Line coverage of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Efficient Path Selection for Delay Testing Based on Path Clustering
Journal of Electronic Testing: Theory and Applications
A Statistical Model for Delay-Fault Testing
IEEE Design & Test
An Exact Non-Enumerative Fault Simulator for Path-Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Bounding Circuit Delay by Testing a Very Small Subset of Paths
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
ENHANCED DELAY DEFECT COVERAGE WITH PATH-SEGMENTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Finding a Small Set of Longest Testable Paths that Cover Every Gate
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme
ITC '02 Proceedings of the 2002 IEEE International Test Conference
The path-status graph with application to delay fault simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path delay fault diagnosis and coverage-a metric and an estimation technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay fault coverage, test set size, and performance trade-offs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper we analyze the coverage of distributed delaydefects, on untested but functionally sensitizable paths,achieved by robustly testing a subset of paths in the circuit.This is measured by translating the information gained fromrobust testing into a set of linear constraints on edge delaysand then using these to bound the circuit delay. Surprisingly,the results of our experiments on ISCAS benchmarkcircuits show that robust testing of a subset of paths in thecircuit, may not cover distributed delay defects on the remainingpaths very well at all.