Enhancing test efficiency for delay fault testing using multiple-clocked schemes
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
On theoretical and practical considerations of path selection for delay fault testing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
TESTING OF CRITICAL PATHS FOR DELAY FAULTS
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Speed Binning with Path Delay Test in 150-nm Technology
IEEE Design & Test
What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit?
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Static statistical timing analysis for latch-based pipeline designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Experience in critical path selection for deep sub-micron delay test and timing validation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Transition path delay faults: a new path delay fault model for small and large delay defects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosis framework for locating failed segments of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Residue arithmetic for variation-tolerant design of multiply-add units
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in nature can affect the performance of deep sub-micron designs. In order to capture the effects of these statistical variations on circuit performance, we incorporate statistical information in timing analysis to compute the performance sensitivity of internal signals subject to a given type of defect, noise or variation sources.We further propose a novel path and segment selection methodology for delay testing based on the results of statistical performance sensitivity analysis. The objective of path/segment selection is to identify a small set of paths and segments such that the delay tests for the selected paths/segments guarantee the detection of performance failure caused by the target type of defect, noise or variation source. This new path selection methodology defines a new path/segment-searching paradigm for detecting delay faults in deep sub-micron devices.