Path delay test compaction with process variation tolerance
Proceedings of the 42nd annual Design Automation Conference
Detection of multiple transitions in delay fault test of SPARC64 microprocessor
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A dynamic test compaction procedure for high-quality path delay testing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
| Hi-index | 0.01 |
This paper develops an improved approach for hierarchicalfunctional test generation for complex chips. In orderto deal with the increasing complexity of functional testgeneration, hierarchical approaches have been suggestedwherein functional constraints are extracted for each moduleunder test (MUT) within a design. These constraintsdescribe a simplified ATPG view for the MUT and therebyspeed up the test generation process. This paper developsan improved approach which applies this technique atdeeper levels of hierarchy, so that effective tests can bedeveloped for large designs with complex submodules. Atool called FACTOR (FunctionAl ConsTraint extractOR),which implements this methodology is described in thiswork. Results on the ARM design prove the effectiveness ofFACTOR-ising large designs for test generation and testabilityanalysis.