VIPER: an efficient vigorously sensitizable path extractor
DAC '93 Proceedings of the 30th international Design Automation Conference
The kernel, the bargaining set and the reduced game
International Journal of Game Theory
An advanced diagnostic method for delay faults in combinational faulty circuits
Journal of Electronic Testing: Theory and Applications
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An efficient automatic test generation system for path delay faults in combinational circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
IEEE Design & Test
Delay Fault Coverage Enhancement Using Variable Observation Times
Journal of Electronic Testing: Theory and Applications
A testability metric for path delay faults and its application
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Multiple Scan Chain Design for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications
9.2 On Delay-Untestable Paths and Stuck-Fault Redundancy
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
On Selecting Testable Paths in Scan Designs
Journal of Electronic Testing: Theory and Applications
Scalable Delay Fault BIST for Use with Low-Cost ATE
Journal of Electronic Testing: Theory and Applications
TranGen: a SAT-based ATPG for path-oriented transition faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A new classification of path-delay fault testability in terms of stuck-at faults
Journal of Computer Science and Technology
Propagation delay fault: a new fault model to test delay faults
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Scaling of iDDT Test Methods for Random Logic Circuits
Journal of Electronic Testing: Theory and Applications
Critical Path Selection for Delay Testing Considering Coupling Noise
Journal of Electronic Testing: Theory and Applications
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We propose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and a falling transition. However, the test criterion is different from that of the slow-to-rise and slow-to-fall transition faults. The test, called "line delay test", is a path delay test for the longest sensitizable path producing a given transition on the target line. The maximum number of tests (and faults) is limited to twice the number of lines. However, the line delay test criterion resembles path delay test and not the gate or transition delay test. Using a two-pass test generation procedure, we begin with a minimal set of longest paths covering all lines and generate tests for them. Fault simulation is used to determine the coverage metric. For uncovered lines, in the second pass, several paths of decreasing length are targeted. We present a theorem stating that a redundant stuck-at fault makes all path delay faults involving the faulty line untestable for either a rising or falling transition depending on the type of the stuck-at fault. The use of this theorem considerably reduces the effort of delay test generation. We give results on benchmark circuits.