Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Line coverage of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Testing of critical paths for delay faults
Proceedings of the IEEE International Test Conference 2001
AC Test Quality: Beyond Transition Fault Coverage
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
On test coverage of path delay faults
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Tutorial: Delay Fault Models and Coverage
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Segment delay faults: a new fault model
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Finding a Small Set of Longest Testable Paths that Cover Every Gate
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay Fault Diagnosis for Non-Robust Test
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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A new fault model, named propagation delay fault model, is proposed to test the gross gate delay defects modeled at each gate terminal and the distributed delay defects in the fault propagation paths. The proposed fault model assumes that the sum of the gross gate delay defect and the distributed delay defect are large enough to cause timing violation for all the paths passing through the fault site and the fault propagation path. Experimental results demonstrate that high fault coverage can be achieved in a reasonable amount of time and the test set size is comparable to the test set size generated for the transition fault model.