Equivalence of robust delay-fault and single stuck-fault test generation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Efficient Identification of Non-Robustly Untestable Path Delay Faults
Proceedings of the IEEE International Test Conference
Effective Path Selection for Delay Fault Testing of Sequential Circuits
Proceedings of the IEEE International Test Conference
Redundancy Identification Using Transitive Closure
ATS '96 Proceedings of the 5th Asian Test Symposium
On test coverage of path delay faults
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Identifying Redundant Path Delay Faults in Sequential Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Primitive Path Delay Fault Identification
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Identifying sequentially untestable faults using illegal states
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Exploiting multicycle false paths in the performance optimization of sequential logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational ATPG theorems for identifying untestable faults in sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
False-Path Removal Using Delay Fault Simulation
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
A new classification of path-delay fault testability in terms of stuck-at faults
Journal of Computer Science and Technology
| Hi-index | 0.00 |
We explore non-robust untestability of paths based on redundant stuck-at faults. Such untestability classification is necessary for a path to be ignored in timing verification and delay testing. A recent result states that redundant stuck-at-0 (s-a-0) and stuck-at-1 (sa-1) faults of a line imply untestability of rising and falling delay faults, respectively, for all paths through that line. We find that this result only establishes robust untestability of paths. Starting with known examples, where a non-robust test can exist for some paths that pass through the site of a redundant stuck-at fault, we examine various classes of stuck-at fault redundancies. We prove that: (1) an unexcitable or undrivable redundant s-a-0 (s-a-1) fault will make all paths through the fault site non-robustly delay-untestable for rising (falling) transition, and (2) an unobservable fault site (causing both s-a-0 and s-a-1 faults to be redundant) can only classify the passing paths as robustly delay-untestable. Finally, we show that two singly-untestable paths, passing through the sites of separate redundant single stuck-at faults, may form a multiply-testable pair of paths provided the two redundant single stuck-at faults have a multifault test.