Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Equivalence of robust delay-fault and single stuck-fault test generation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
On local transformations and path delay fault testability
Journal of Electronic Testing: Theory and Applications
A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits
IEEE Transactions on Computers
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Exact Non-Enumerative Fault Simulator for Path-Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
Efficient Identification of Non-Robustly Untestable Path Delay Faults
Proceedings of the IEEE International Test Conference
A non-enumerative path delay fault simulator for sequential circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Redundancy Identification Using Transitive Closure
ATS '96 Proceedings of the 5th Asian Test Symposium
False-Path Removal Using Delay Fault Simulation
ATS '98 Proceedings of the 7th Asian Test Symposium
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
9.2 On Delay-Untestable Paths and Stuck-Fault Redundancy
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
| Hi-index | 0.00 |
Some false paths are caused by redundant stuck-at faults. Removal of those stuck-at faults automatically eliminates such false paths from the circuit. However, there are other false paths that are not associated with any redundant stuck-at fault. All segments of such a false path are shared with other testable paths. We focus on the elimination of this type of false paths. We use a non-enumerative path delay fault simulator based on the path status graph (PSG) data-structure, which duplicates selected gates to separate the detected and undetected path delay faults. The expanded circuit may contain new redundant stuck-at faults, corresponding to those undetected paths that are false. This happens because the expanded circuit has some new interconnects with only false paths passing through them. Such links become the sites for redundant stuck-at faults. Removal of these redundant faults eliminates false paths. The reported results show that the quality of the result may depend on the coverage of testable paths by the vectors that are simulated. When non-enumerative path delay simulation and implication-based redundancy removal techniques are used, the present procedure of false-path elimination can be applied to very large circuits.