A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits

Authors:
Sreejit Chakravarty
Affiliations:
-
Venue:
IEEE Transactions on Computers
Year:
1996

Citing 4
Cited 1

Introduction to mathematical logic (3rd ed.)

Introduction to mathematical logic (3rd ed.)
Equivalence of robust delay-fault and single stuck-fault test generation

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Testability properties of multilevel logic networks derived from binary decision diagrams

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Achieving Complete Delay Fault Testability by Extra Inputs

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False-Path Removal Using Delay Fault Simulation

Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98

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Abstract

Multilevel Logic Optimization Transformations used in existing logic synthesis systems are characterized with respect to their testability preserving and testability enhancing properties. A sufficient condition for a multilevel unate circuit to be "hazard free delay fault testable" is presented. In contrast to existing results that consider either "single path propagating hazard free robust tests" or "general robust tests" we consider "multiple path propagating hazard free robust tests" in our analysis.