Testability properties of multilevel logic networks derived from binary decision diagrams

A synthesis-based test generation and compaction algorithm for multifaults

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference

A time optimal robust path-delay-fault self-testable adder

EURO-DAC '92 Proceedings of the conference on European design automation

Design-for-testability for path delay faults in large combinatorial circuits using test-points

DAC '94 Proceedings of the 31st annual Design Automation Conference

On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits

IEEE Transactions on Computers

A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits

IEEE Transactions on Computers

A Characterization of Binary Decision Diagrams

IEEE Transactions on Computers

MuTaTe: an efficient design for testability technique for multiplexor based circuits

Proceedings of the 13th ACM Great Lakes symposium on VLSI