Efficient Testing of Optimal Time Adders
IEEE Transactions on Computers
Testability properties of multilevel logic networks derived from binary decision diagrams
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Journal of the ACM (JACM)
A Fast Optimal Robust Path Delay Fault Testable Adder
EDTC '96 Proceedings of the 1996 European conference on Design and Test
(Quasi-) Linear Path Delay Fault Tests for Adders
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
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