Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Testability properties of multilevel logic networks derived from binary decision diagrams
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Path-delay-fault testability properties of multiplexor-based networks
Integration, the VLSI Journal
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Testing with decision diagrams
Integration, the VLSI Journal - Special issue on VLSI testing
Wave steering in YADDs: a novel non-iterative synthesis and layout technique
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ACTion: combining logic synthesis and technology mapping for MUX-based FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
On-the-fly layout generation for PTL macrocells
Proceedings of the conference on Design, automation and test in Europe
Synthesis for Testability: Binary Decision Diagrams
STACS '92 Proceedings of the 9th Annual Symposium on Theoretical Aspects of Computer Science
Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
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We present a technique to derive fully testable circuits under the Stuck-At Fault Model (SAFM) and the Path-Delay Fault Model (PDFM). Starting from a function description as a Binary Decision Diagram (BDD) the netlist is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under SAFM and PDFM. Experiments are given to show the advantages of the the technique in comparison to previously presented methods.