VIPER: an efficient vigorously sensitizable path extractor
DAC '93 Proceedings of the 30th international Design Automation Conference
The kernel, the bargaining set and the reduced game
International Journal of Game Theory
Test generation for resistive opens in CMOS
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Generating Tests for Delay Faults in Nonscan Circuits
IEEE Design & Test
Test Generation for Global Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Skewed-Load Transition Test: Part 1, Calculus
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
Timing Verification and Delay Test Generation for Hierarchical Designs
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Accounting for electrical phenomena in delay fault testing
Accounting for electrical phenomena in delay fault testing
IEEE Design & Test
A new classification of path-delay fault testability in terms of stuck-at faults
Journal of Computer Science and Technology
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Existing delay test generation techniques focus on testgeneration for combinational blocks, and assume the inputsand outputs of the block to be unconstrained. Test applicationfor delay tests is done by means of enhanced scan, scanshifting or functional justification; all these techniques imposeminimal constraints on the inputs and the outputs ofthe combinational block targeted. This leads to over-testingthe components for delay defects [11]. This paper analyzesthe gains associated with determining the multi-cycle (sequential)sensitization of delay tests. The advantages ofdetermining multi-cycle sensitization is then illustrated onbenchmark designs with and without a delay-specific faultmodel.