DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
IDDQ and AC Scan: The War Against Unmodelled Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
A delay fault model for at-speed fault simulation and test generation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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In this paper, we describe a new transition fault model for synchronous sequential circuits. Similar to previous models, it addresses the fact that delayed signal-transitions span multiple clock cycles when a test sequence is applied at-speed. It addresses this issue in a different way than earlier models. The model requires the activation of single stuck-at faults with opposite stuck-at values on the same line g at consecutive time units. In addition, it requires the detection of both faults (as single faults) at the same or later time units. Due to the activation of the faults at consecutive time units, there is a 1 → 0 or 0 → 1 transition at the fault site g. Since both faults are eventually detected, a deviation from the expected value at either the first or second time unit due to a delay fault on g or due to transitions that started earlier and did not settle will be (or is likely to be) detected. The model can be used together with other models to increase the confidence that delay defects will be detected. As an added advantage, the model helps detect other types of faults that require two-pattern tests, such as transistor stuck-open faults.