Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
Modeling and testing the Gekko microprocessor, an IBM PowerPC derivative for Nintendo
Proceedings of the IEEE International Test Conference 2001
A 1.3GHz fifth generation SPARC64 microprocessor
Proceedings of the 40th annual Design Automation Conference
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Delay Defect Characteristics and Testing Strategies
IEEE Design & Test
A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Detection of multiple transitions in delay fault test of SPARC64 microprocessor
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
LOW OVERHEAD DELAY TESTING OF ASICS
ITC '04 Proceedings of the International Test Conference on International Test Conference
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This paper presents a case-study of delay defect screening applied to Fujitsu 2.16GHz SPARC64 microprocessor. A non-robust delay test is used while each test vector is compacted to detect multiple transition faults in a standard scan-based design targeting a stuck-at fault test. Our test technique applied to a microprocessor designed with 6M gate logic, 4MB level 2 cache, and 239K latches, achieves 90% coverage using 3,103 test vectors. We estimate the distribution of the delay of paths covered by our delay test. We also show the effectiveness of our method by discussing the correlation between the screening result and the actual number of delay defects.