Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
Scan BIST Targeting Transition Faults Using a Markov Source
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Proceedings of the 41st annual Design Automation Conference
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Constraint extraction for pseudo-functional scan-based delay testing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Functional constraints vs. test compression in scan-based delay testing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Deterministic Logic BIST for Transition Fault Testing
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
An Approach to Minimizing Functional Constraints
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
On reset based functional broadside tests
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generation of Functional Broadside Tests for Transition Faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Complete Functional Broadside Tests for Transition Faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Built-in generation of multicycle functional broadside tests with observation points
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design-for-testability for multi-cycle broadside tests by holding of state variables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Functional broadside tests are two-pattern scanbased tests that avoid overtesting by ensuring that a circuit traverses only reachable states during the functional clock cycles of a test. In addition, the power dissipation during the fast functional clock cycles of functional broadside tests does not exceed that possible during functional operation. On-chip test generation has the added advantage that it reduces test data volume and facilitates at-speed test application. This paper shows that on-chip generation of functional broadside tests can be done using a simple and fixed hardware structure, with a small number of parameters that need to be tailored to a given circuit, and can achieve high transition fault coverage for testable circuits. With the proposed on-chip test generation method, the circuit is used for generating reachable states during test application. This alleviates the need to compute reachable states offline.