On yield, fault distributions, and clustering of particles
IBM Journal of Research and Development
Correlation analysis of particle clusters on integrated circuit wafers
IBM Journal of Research and Development
Modeling Defect Spatial Distribution
IEEE Transactions on Computers
Small-area fault clusters and fault tolerance in VLSI circuits
IBM Journal of Research and Development
Synergistic Fault-Tolerance for Memory Chips
IEEE Transactions on Computers
A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits
IEEE Transactions on Computers
Improved Yield Model for Submicron Domain
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Quality-Effective Repair of Multichip Module Systems
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Novel yield model for integrated circuits with clustered defects
Expert Systems with Applications: An International Journal
An ROBDD-based combinatorial method for the evaluation of yield of defect-tolerant systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Expert Systems with Applications: An International Journal
Expert Systems with Applications: An International Journal
Communication in networks with random dependent faults
MFCS'07 Proceedings of the 32nd international conference on Mathematical Foundations of Computer Science
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This work addresses the problem of predicting the yield of a chip composed of cores. A center-satellite model is used to directly represent observed spatial autocorrelation of integrated circuit spot defects. This model is compared to another (large-area clustering) model that only indirectly represents intrawafer correlation. We illustrate that, when different portions of a chip have different susceptibility to defects, the chip layout will affect the predicted yield. This is particularly relevant when portions of a chip are defect-tolerant because their susceptibility to defects is dramatically different. We illustrate how the yield models can be used to predict the utility of making much of a chip (or an embedded core) defect-tolerant. Two yield points parameterized the models. The one extra parameter of, and the suitability of, the center-satellite model allowed it to track the yield data points with less than 1/10,000 of the error of the large-area clustering model. However, the simpler large-area clustering model is accurate in some circumstances, especially when the chip area is small.