Novel yield model for integrated circuits with clustered defects

Authors:
Lee-Ing Tong;Li-Chang Chao
Affiliations:
Department of Industrial Engineering and Management, National Chiao Tung Uninversity, 1001 Dah-Hsei Road, Hsin-Chu 300, Taiwan, ROC;Department of Industrial Engineering and Management, National Chiao Tung Uninversity, 1001 Dah-Hsei Road, Hsin-Chu 300, Taiwan, ROC
Venue:
Expert Systems with Applications: An International Journal
Year:
2008

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Abstract

As wafer sizes increase, the clustering phenomenon of defects increases. Clustered defects cause the conventional Poisson yield model underestimate actual wafer yield, as defects are no longer uniformly distributed over a wafer. Although some yield models, such as negative binomial or compound Poisson models, consider the effects of defect clustering on yield prediction, these models have some drawbacks. This study presents a novel yield model that employs General Regression Neural Network (GRNN) to predict wafer yield for integrated circuits (IC) with clustered defects. The proposed method utilizes five relevant variables as input for the GRNN yield model. A simulated case is applied to demonstrate the effectiveness of the proposed model.