Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
On yield, fault distributions, and clustering of particles
IBM Journal of Research and Development
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits
IEEE Transactions on Computers
The Size of Reduced OBDD's and Optimal Read-Once Branching Programs for Almost all Boolean Functions
IEEE Transactions on Computers
Tighter Bounds on Full Access Probability in Fault-Tolerant Multistage Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
On the Yield of VLSI Processors with On-Chip CPU Cache
IEEE Transactions on Computers
Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy
IEEE Transactions on Computers
Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Dependability Assessment Using Binary Decision Diagrams (BDDs)
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Predicting Defect-Tolerant Yield in the Embedded Core Context
IEEE Transactions on Computers
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Guest Editors' Introduction: Design for Yield and Reliability
IEEE Design & Test
Micro-Network for SoC: Implementation of a 32-Port SPIN network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC)
IEEE Transactions on Computers
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Yield prediction by sampling IC layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
In this paper, we develop a combinatorial method for the evaluation of the functional yield of defect-tolerant systems-on-chip (SoC). The method assumes that random manufacturing defects are produced according to a model in which defects cause the failure of given components of the system following a distribution common to all defects. The distribution of the number of defects is arbitrary. The yield is obtained by conditioning on the number of defects that result in the failure of some component and performing recursive computations over a reduced ordered binary decision diagram (ROBDD) representation of the fault-tree function of the system. The method has excellent error control. Numerical experiments seem to indicate that the method is efficient and, with some exceptions, allows the analysis with affordable computational resources of systems with very large numbers of components.