Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs

  • Authors:
  • Israel Koren;Zahava Koren

  • Affiliations:
  • -;-

  • Venue:
  • DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
  • Year:
  • 1997

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Abstract

Recent increases in the density and size of memory ICs made it necessary to search for new defect tolerance techniques since the traditional methods are no longer effective enough. Several new such schemes have been recently proposed and implemented. Due to the high complexity of these new techniques compared to the simple row and column redundancy, Monte-Carlo simulations were used to evaluate their yield enhancement. In this paper we present a yield analysis of one such new design and compare its yield to that of the traditional design.