Improved Yield Model for Submicron Domain

Authors:
Witold A. Pleskacz;Wojciech Maly
Affiliations:
-;-
Venue:
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Year:
1997

Citing 0
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Abstract

This paper describes a new manufacturing yield model for submicron VLSI circuits. This model attempts to handle process induced differences between IC layout and actual IC topography. The presented model focuses on the random nature of over and under etching phenomenon. The relevance of the new yield model in submicron domain is analyzed. Examples of yield calculations using the proposed model are presented as well.