A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
Fault Detection and Fault Diagnosis Technoques for Lookup Table FPGA's
ATS '02 Proceedings of the 11th Asian Test Symposium
Testing and Diagnosis Techniques for LUT-Based FPGA's
ATS '04 Proceedings of the 13th Asian Test Symposium
Hierarchical Built-in Self-testing and FPGA Based Healing Methodology for System-on-a-Chip
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
Applying dynamic reconfiguration for fault tolerance in fine-grained logic arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper we propose a fault model for Programmable Logic Array in which defects appear in programmable elements. The classical models by which the faults in PLA are described (stuck-at-fault, bridging faults and cross point fault model) do not describe the defects which can appear in the programmable elements of PLA. We propose a fault model for PLA in which programmable elements where faults appear get the signal values of permanent logic 1 or permanent logic 0. We also developed a procedure for detecting a multiple fault located at the programmable elements of PLA. The testing procedure makes use of the path sensitization method. It is illustrated by some examples. By the proposed procedure a number of stuck-at-faults, bridging faults and cross point faults are detected as well.