Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits

Authors:
Y. Savaria;C. Thibeault;J. l. Houle
Affiliations:
-;-;-
Venue:
IEEE Transactions on Computers
Year:
1995

Citing 3
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Abstract

In this paper, two equivalence proofs of yield modeling methods for defect-tolerant integrated circuits (ICs) are presented. These proofs are generalizations of those found in [3]; one of the proofs presented in this paper is valid for any defect-tolerant IC, while the other one is valid for defect-tolerant ICs with two levels of hierarchy.