Introduction to VLSI Systems
The Power of a One-Dimensional Vector of Processors
WG '80 Proceedings of the International Workshop on Graphtheoretic Concepts in Computer Science
Fault-tolerant wafer-scale architectures for VLSI
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
A reconfigurable and fault-tolerant VLSI multiprocessor array
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
How to assemble tree machines (Extended Abstract)
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
A model of computation for VLSI with related complexity results
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
Area-efficient vlsi computation
Area-efficient vlsi computation
An Approach to Highly Integrated, Computer-Maintained Cellular Arrays
IEEE Transactions on Computers
A Graph Model for Fault-Tolerant Computing Systems
IEEE Transactions on Computers
A Dictionary Machine (for VLSI)
IEEE Transactions on Computers
On Embedding Rectangular Grids in Square Grids
IEEE Transactions on Computers
Wafer-scale integration of systolic arrays
SFCS '82 Proceedings of the 23rd Annual Symposium on Foundations of Computer Science
A Fault-Tolerant Modular Architecture for Binary Trees
IEEE Transactions on Computers - The MIT Press scientific computation series
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
IEEE Transactions on Computers
Efficient embeddings of binary trees in VLSI arrays
IEEE Transactions on Computers
Optimal Graph Algorithms on a Fixed-Size Linear Array
IEEE Transactions on Computers
Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance
IEEE Transactions on Computers
A Generalized Theory for System Level Diagnosis
IEEE Transactions on Computers
Gracefully Degradable Pipeline Networks
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
An improved approach to fault tolerant rank order filtering on a SIMD mesh processor
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Totally defect-tolerant arrays capable of quick broadcasting
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
On the pagenumber of planar graphs
STOC '84 Proceedings of the sixteenth annual ACM symposium on Theory of computing
Queue layouts of iterated line directed graphs
Discrete Applied Mathematics
An improved upper bound on the queuenumber of the hypercube
Information Processing Letters
Approximating the fixed linear crossing number
Discrete Applied Mathematics
Improved book-embeddings of incomplete hypercubes
Discrete Applied Mathematics
Upper bounds on the queuenumber of k-ary n-cubes
Information Processing Letters
Evaluation of system BIST using computational performance measures
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On the page number of upward planar directed acyclic graphs
GD'11 Proceedings of the 19th international conference on Graph Drawing
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This paper describes by a series of examples a strategy for designing testable fault-tolerant arrays of processors. The strategy achieves fault tolerance by introducing redundancy in an array's communication links rather than in its processing elements (PE's). The major characteristics of the designs produced are as follows.