Introduction to VLSI Systems
The Power of a One-Dimensional Vector of Processors
WG '80 Proceedings of the International Workshop on Graphtheoretic Concepts in Computer Science
SFCS '80 Proceedings of the 21st Annual Symposium on Foundations of Computer Science
A Fault-Tolerant Modular Architecture for Binary Trees
IEEE Transactions on Computers - The MIT Press scientific computation series
Large-Capacity High-Throughput Low-Cost Pipelined CAM Using Pipelined CTAM
IEEE Transactions on Computers
The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors
IEEE Transactions on Computers
An Efficient Implementation of Search Trees on [lg N + 1] Processors
IEEE Transactions on Computers
A Systolic Design for Connectivity Problems
IEEE Transactions on Computers
| Hi-index | 14.99 |
We present the design of a dictionary machine that is suitable for VLSI implementation, and we discuss how to realize this implementation efficiently. The machine supports the operations of SEARCH, INSERT, DELETE, and EXTRACTMIN on an arbitrary ordered set. Each of these operations takes time O(log n), where n is the number of entries present when the operation is performed. Moreover, arbitrary sequences of these instructions can be pipelined through the machine at a constant rate (i.e., independent of n and the capacity of the machine). The time O(log n) is an improvement over previous VLSI designs of dictionary machines which require time O(log N) per operation, where N is the maximum number of keys that can be stored.