Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
A Cube-Connected Cycles Architecture with High Reliability and Improved Performance
IEEE Transactions on Computers
Fault-Tolerant Meshes and Hypercubes with Minimal Numbers of Spares
IEEE Transactions on Computers
A Graph Model for Fault-Tolerant Computing Systems
IEEE Transactions on Computers
The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors
IEEE Transactions on Computers
Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring
IEEE Transactions on Computers
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This paper proposes an advanced spare-connection scheme for k-out-of-n redundancy called "generalized additional bypass linking (ABL)" for total defect-tolerance in large hybrid-WSIs with array structures. The proposed scheme uses bypass links with wired-OR connections to spare processing elements (PEs) without external switches, and can reconfigure complete arrays by tolerating defects in these PEs, links, and external I/O-terminals. The wired-OR connections help to limit the increase in the PE-connections of spare PEs, and these connections are made so that the primary PEs are an inter-PE distance of 3 or more away from each other and are connected to the same bypass link in parallel. The ABL scheme can be used for constructing totally defect-tolerant (TDT) arrays capable of quick broadcasting by using spare circuitries, and it is superior to conventional schemes in terms of extra PE-connections and control of the reconfiguration. This paper describes the basic ABL configurations for series-connected arrays, two-dimensional mesh-connected arrays, and binary trees, and further describes a hierarchical application of the ABL scheme that allows the construction of large arrays using shorter bypass links than the basic ABL configurations.