Configuration of VLSI Arrays in the Presence of Defects
Journal of the ACM (JACM)
Data structures and network algorithms
Data structures and network algorithms
Tight bounds for minimax grid matching, with applications to the average case analysis of algorithms
STOC '86 Proceedings of the eighteenth annual ACM symposium on Theory of computing
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
IEEE Transactions on Computers
Applications of slack neighborhood graphs to timing driven optimization problems in FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Re-engineering of timing constrained placements for regular architectures
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Efficient algorithms for finding disjoint paths in grids
SODA '97 Proceedings of the eighth annual ACM-SIAM symposium on Discrete algorithms
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 14.98 |
A technique for reconfiguring a two-dimensional VLSI array with faulty cells is presented. A network flow model of the problem is used to provide an algorithm for connecting the functional cells of the array so that they simulate a fault-free array of smaller size. The interconnection wires are routed inside horizontal and vertical channels according to the Manhattan model. Experimental results indicate that the algorithm has good performance in practice.