The architecture and programming of the Ametek series 2010 multicomputer
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
Distributing resources in hypercube computers
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy
IEEE Transactions on Computers
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Tolerating Faults in Hypercubes Using Subcube Partitioning
IEEE Transactions on Computers - Special issue on fault-tolerant computing
The J-machine multicomputer: an architectural evaluation
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Channel multiplexing in fault-tolerant modular multiprocessors
Journal of Parallel and Distributed Computing
Topics in toroidal interconnection networks
Topics in toroidal interconnection networks
Fault-Tolerant Meshes and Hypercubes with Minimal Numbers of Spares
IEEE Transactions on Computers
Reconfiguring Processor Arrays Using Multiple-Track Models: The 3Track-Spare-Approach
IEEE Transactions on Computers
Design and Evaluation of Hardware Strategies for Reconfiguring Hypercubes and Meshes Under Faults
IEEE Transactions on Computers
Lee Distance and Topological Properties of k-ary n-cubes
IEEE Transactions on Computers
Free Dimensions-An Effective Approach to Achieving Fault Tolerance in Hypercubes
IEEE Transactions on Computers
Resource Placement in Torus-Based Networks
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
A Graph Model for Fault-Tolerant Computing Systems
IEEE Transactions on Computers
Resource Placement in Torus-Based Networks
IEEE Transactions on Computers
IEEE Transactions on Computers
Enhanced Cluster k-Ary n-Cube, A Fault-Tolerant Multiprocessor
IEEE Transactions on Computers
On resource placements in 3D tori
Journal of Parallel and Distributed Computing - Special section best papers from the 2002 international parallel and distributed processing symposium
Perfect Distance-d Placements in 2D Toroidal Networks
The Journal of Supercomputing
An efficient reconfiguration scheme for fault-tolerant meshes
Information Sciences—Informatics and Computer Science: An International Journal
Quasi-perfect resource placements for two-dimensional toroidal networks
Journal of Parallel and Distributed Computing
Efficient Subtorus Processor Allocation in a Multi-Dimensional Torus
HPCASIA '05 Proceedings of the Eighth International Conference on High-Performance Computing in Asia-Pacific Region
Chromatic sets of power graphs and their application to resource placement in multicomputer networks
Computers & Mathematics with Applications
An efficient reconfiguration scheme for fault-tolerant meshes
Information Sciences: an International Journal
Resource placement in Cartesian product of networks
Journal of Parallel and Distributed Computing
Resource placement in networks using chromatic sets of power graphs
CSR'07 Proceedings of the Second international conference on Computer Science: theory and applications
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Some fault-tolerant architectures use the spare nodes or links to replace the faulty components. This paper gives solutions to spare processor placement problem for torus based networks. Optimal 1-hop spare processor placement methods for multi-dimensional tori and t-hop placement methods for 2D tori are described. In the presence of node failures, a system reconfiguration scheme using spare nodes is also given.