IEEE Transactions on Computers
The connection machine
On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures
IEEE Transactions on Computers
Designing fault-tolerant systems using automorphisms
Journal of Parallel and Distributed Computing
Designing and reconfiguring fault-tolerant multiprocessor systems
Designing and reconfiguring fault-tolerant multiprocessor systems
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
Distributed fault-tolerance for large multiprocessor systems
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Systematic Design of Fault-Tolerant Multiprocessors with Shared Buses
IEEE Transactions on Computers
Node-covering, Error-correcting Codes and Multiprocessors with Very High Average Fault Tolerance
IEEE Transactions on Computers
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring
IEEE Transactions on Computers
IEEE Transactions on Computers
Computing in the RAIN: A Reliable Array of Independent Nodes
IEEE Transactions on Parallel and Distributed Systems
Modular Fault-Tolerant Boolean N-Cubes
IEEE Micro
Survivable Computer Networks in the Presence of Partitioning
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
A Limited-Global Fault Information Model for Dynamic Routing in 2-D Meshes
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Spare processor allocation for fault tolerance in torus-based multicomputers
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Origin-based fault-tolerant routing in the mesh
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Node Covering, Error Correcting Codes and Multiprocessors with Very High Average Fault Tolerance
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Tolerant Switched Local Area Networks
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
A Proxy-Network Based Overlay Topology Resistant to DoS Attacks and Partitioning
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 16 - Volume 17
Extended minimal routing in 2-D meshes with faulty blocks
International Journal of High Performance Computing and Networking
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Methods for modeling and implementing various practical aspects of fault-tolerant multiprocessor systems largely neglected in prior research are examined. The node-covering design approach is generalized to accommodate systems whose structure and failure mechanisms are represented by arbitrary graphs. Several new types of covering graphs are defined, which lead to various useful design tradeoffs. A new technique for incremental design is presented, using a class of switch implementations that reduce a system's interconnection costs. The reduction of other cost factors is also addressed, and methods are presented for VLSI layout area minimization, fast and distributed reconfiguration, efficient transfer of state information for software recovery, and the efficient use of local spares.