An efficient reconfiguration scheme for fault-tolerant meshes

Authors:
Po-Jen Chuang;Li-Chiang Yao
Affiliations:
Department of Electrical Engineering, Tamkang University, Tamsui, Taipei Hsien, Taiwan 25137, ROC;Department of Electrical Engineering, Tamkang University, Tamsui, Taipei Hsien, Taiwan 25137, ROC
Venue:
Information Sciences—Informatics and Computer Science: An International Journal
Year:
2005

Citing 13
Cited 3

Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays

IEEE Transactions on Computers
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor

IEEE Transactions on Computers
Designing fault-tolerant systems using automorphisms

Journal of Parallel and Distributed Computing
Systematic Design of Fault-Tolerant Multiprocessors with Shared Buses

IEEE Transactions on Computers
Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring

IEEE Transactions on Computers
Fault-Tolerant Processor Arrays Based on the 1$\frac{1}{2}$-Track Switches with Flexible Spare Distributions

IEEE Transactions on Computers
Design and Evaluation of Hardware Strategies for Reconfiguring Hypercubes and Meshes Under Faults

IEEE Transactions on Computers
An Efficient Modular Spare Allocation Scheme and Its Application to Fault Tolerant Binary Hypercubes

IEEE Transactions on Parallel and Distributed Systems
Routing in Modular Fault-Tolerant Multiprocessor Systems

IEEE Transactions on Parallel and Distributed Systems
Design of a Circuit-Switched Highly Fault-Tolerant k-ary n-cube

ICPP '97 Proceedings of the international Conference on Parallel Processing
Built-in Self-Reconfiguring Systems for Fault Tolerant Mesh-Connected Processor Arrays by Direct Spare Replacement

DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Spare processor allocation for fault tolerance in torus-based multicomputers

FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Reconfigurable Mesh-Connected Processor Arrays Using Row-Column Bypassing and Direct Replacement

ISPAN '00 Proceedings of the 2000 International Symposium on Parallel Architectures, Algorithms and Networks

Immucube: Scalable Fault-Tolerant Routing for k-ary n-cube Networks

IEEE Transactions on Parallel and Distributed Systems
Constructing vertex-disjoint paths in (n, k)-star graphs

Information Sciences: an International Journal
An improved replacement algorithm in fault-tolerant meshes

Proceedings of the 2007 Summer Computer Simulation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

A new reconfiguration scheme, including a reconfiguration algorithm, is proposed in this paper to lift up the fault tolerance and system reconfiguration abilities for the mesh topology. The scheme adds redundancies--spare nodes and links--to the mesh network for necessary node replacement. By collocating a suitable number of spare nodes located at the best site of the network and joined by some well-connected spare links, our scheme is simple and yet effective in performing system reconfiguration. To carry out reconfiguration in a more regulated way, a reconfiguration algorithm is provided. The algorithm works dynamically and individually: system reconfiguration starts instantly upon the emergence of a fault and the replacement of a new faulty node is considered independently from previous replacements. Experimental performance evaluation shows that, with significantly reduced complexity, the proposed reconfiguration scheme is able to achieve desirable reconfiguration rates for the mesh network.