The Architecture of Symbolic Computers
The Architecture of Symbolic Computers
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Fault-tolerant wafer-scale architectures for VLSI
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
A reconfigurable and fault-tolerant VLSI multiprocessor array
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
SIMULATION TOOLS FOR DIGITAL LSI DESIGN
SIMULATION TOOLS FOR DIGITAL LSI DESIGN
Computational Aspects of VLSI
Harvest Rate of Reconfigurable Pipelines
IEEE Transactions on Computers
Paper: Reconfigurable VLSI/WSI multipipelines
Parallel Computing
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The problem of recovering multipipelines in the presence of faulty stages is addressed. The stages are assumed to be organized in rows and columns. The pipeline stages are alternated with reconfiguring circuitry which is used for bypassing the faulty stages. The pipelines are configured by programming the switches in a distributed manner using fault information available locally. The configuration algorithm is optimal in the sense that it recovers the maximum number of pipelines under any fault pattern. Probabilistic bounds on the delay (the number of bypassed faulty stages) and yield (the number of nonfaulty pipelines recovered) are derived. It is shown that the maximum signal delay in any of the pipelines is O(log m), where m is the initial number of pipelines. A constant fraction of these pipelines can be recovered with the scheme, as opposed to an exponentially decreasing number when no reconfiguration is used. The reconfiguration scheme can also be used to provide fault-tolerant buses on a wafer.